发明名称 |
Delay locked loop including a mechanism for reducing lock time |
摘要 |
<p>A delay locked loop (DLL) includes a delay line configured to provide a delayed version of a reference clock as a feedback clock. The DLL also includes a phase detector that may provide an output signal that is indicative of a change in a delay associated with the delay line. The DLL may also include a step size controller that may provide a step size indication corresponding to a first step size in response to detecting the output signal indicating a first change in delay, and to provide a step size indications corresponding to a second step size that is smaller than the first step size in response to detecting the output signal indicating a second change in delay.</p> |
申请公布号 |
EP2439848(A1) |
申请公布日期 |
2012.04.11 |
申请号 |
EP20110184522 |
申请日期 |
2011.10.10 |
申请人 |
APPLE INC. |
发明人 |
TRIVEDI, PRADEEP R.;VON KAENEL, VINCENT R. |
分类号 |
H03L7/081;H03L7/089;H03L7/10 |
主分类号 |
H03L7/081 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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