| 摘要 |
The present invention improves the yield of integrated circuit manufacture by making the circuit more tolerant of varying thicknesses of the InterLayer Dielectric prior to metallization and interconnection. The sensitivity to the thickness of the ILD is reduced by first coating the devices with an etch stop layer, exposing the areas of the devices where interconnections will be made, selectively etching away the etch stop layer over the interconnection areas, adding the Interlayer Dielectric and then finally etching away the ILD to expose the contacts and continuing the processing through interconnection of the devices. |
