发明名称 |
High planarizing method for use in a gate last process |
摘要 |
A method for performing a chemical-mechanical polishing (CMP) is provided. The method includes processing a semiconductor substrate to form a dummy gate structure on the substrate, to form a hard mask on the dummy gate structure, and to form a contact etch stop layer (CESL) and an interlayer dielectric (ILD) layer on the hard mask, performing a first CMP process with a first slurry to modify a non-planar topography of the ILD layer, performing a second CMP process with a second slurry to remove the hard mask, and performing a third CMP process with a third slurry to remove an interfacial layer that forms between the dummy gate and hard mask during semiconductor processing. |
申请公布号 |
US8153526(B2) |
申请公布日期 |
2012.04.10 |
申请号 |
US20090499439 |
申请日期 |
2009.07.08 |
申请人 |
LEE SHEN-NAN;LIN HUAN-JUST;CHEN SHIH-CHANG;TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
发明人 |
LEE SHEN-NAN;LIN HUAN-JUST;CHEN SHIH-CHANG |
分类号 |
H01L21/302;B24B37/04;H01L21/461 |
主分类号 |
H01L21/302 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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