| 摘要 |
Methods and apparatus are provided for measuring a delay through one or more transistors in an array of transistors. The delay through one or more transistors in an array of transistors is measured by selecting one of the transistors in the array; and applying a clock signal to the selected transistor, wherein an output of the selected transistor is applied to a first input of a logic gate having at least two inputs and wherein a second clock signal based on the clock signal is applied to a second input of the logic gate, and wherein an output of the logic gate indicates a difference in arrival times of the signals at the two inputs. In one variation, a clock signal is applied to the selected transistor and a variable delay circuit; and an output of the selected transistor is applied to a data input of a latch having a clock input and a data input while an output of the variable delay circuit is applied to a clock input of the latch. The delay applied by the variable delay circuit to the clock signal is adjusted until a predefined transition is detected in an output of the latch. If the delay is measured through a plurality of transistors in the array, the delay variation among the plurality of transistors can be obtained.
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