| 摘要 |
In a conventional DRAM, errors in reading data are likely to occur when the capacitance of a capacitor is reduced. A plurality of cells is connected to one main bit line Each cell includes a sub bit line and 2 to 32 memory cells. Further, each cell includes a selection transistor and a reading transistor, and a sub bit line is connected to a gate of the reading transistor. Since the parasitic capacitance of the sub bit line is sufficiently small, data of electric charge of a capacitor of each memory cell can be amplified without an error in the reading transistor and output to the main bit line.
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