| 摘要 |
Various embodiments of an on-die termination (ODT) signal generating circuit are disclosed. In one exemplary embodiment, the ODT signal generating circuit includes a latency unit and an ODT control signal generating unit. The latency unit is configured to receive a clock signal and an ODT signal. The latency unit is configured to delay the ODT signal by a predetermined time to generate a first ODT signal. The latency unit is also configured to delay the ODT signal by less than the predetermined time to generate a second ODT signal. The ODT control signal generating unit is configured to provide either one of the first and second ODT signals as an ODT control signal in response to a control signal.
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