| 摘要 |
<p>1279314 FET storage circuits TEXAS INSTRUMENTS Inc 15 July 1969 [9 Sept 1968] 35579/69 Heading H3T [Also in Division H1] In an integrated circuit comprising a number of IGFETs the source and drain zones of which are formed by diffusion into a common substrate region of opposite conductivity type, bipolar transistor action caused by the PN junction between any of these zones and the substrate becoming forward biased is reduced by the presence of a diffused collection region adjacent each or all of the regions. The described arrangement, shown in part in Fig. 4, is a capacitive pull-up multi-phase shift register each half-bit of which as shown in Fig. 5 comprises two IGFETs e.g. Q1, Q2 and a capacitor the physical locations of which are marked in Fig. 4. The collector region 80 which surrounds each half-bit forms a continuation of the earthed source electrodes of transistors Q1, Q3. It thus eliminates transistor action between adjacent half-bits and because of its proximity to the source and drain regions of the surrounded transistors greatly reduces it within each halfbit. It may be at the same potential as or reverse biased relative to the substrate and is formed in the same oxide masked diffusion step as the sources and drains. Subsequently after thinning the oxide at the sites of the gates and capacitors the aluminium metallization pattern shown is formed.</p> |
