发明名称 THROUGH SILICON VIA IN N+ EPITAXY WAFERS WITH REDUCED PARASITIC CAPACITANCE
摘要 A semiconductor device includes an epitaxy layer formed on semiconductor substrate, a device layer formed on the epitaxy layer, a trench formed within the semiconductor substrate and including a dielectric layer forming a liner within the trench and a conductive core forming a through-silicon via conductor, and a deep trench isolation structure formed within the substrate and surrounding the through-silicon via conductor. A region of the epitaxy layer formed between the through-silicon via conductor and the deep trench isolation structure is electrically isolated from any signals applied to the semiconductor device, thereby decreasing parasitic capacitance.
申请公布号 US2012080802(A1) 申请公布日期 2012.04.05
申请号 US20100894218 申请日期 2010.09.30
申请人 CHENG KANGGUO;IYER SUBRAMANIAN;KHAKIFIROOZ ALI;KULKARNI PRANITA;INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 CHENG KANGGUO;IYER SUBRAMANIAN;KHAKIFIROOZ ALI;KULKARNI PRANITA
分类号 H01L23/522;H01L21/768 主分类号 H01L23/522
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