INTERRUPT MASKING FOR MULTI-CORE PROCESSORS

摘要

Technologies are generally described herein for handling interrupts within a multi-core processor. A core specific interrupt mask ("CIM") can be adapted to influence the assignment of interrupts to particular processor cores in the multi-core processor. Available processor cores can be identified by evaluating the CIM. An interrupt with an interrupt service routine ("ISR") that is received by the multi-core processor can be assigned to one or more of the available processor cores identified by the CIM.