发明名称 SYSTEM AND METHOD OF CHIP PACKAGE BUILD-UP
摘要 <P>PROBLEM TO BE SOLVED: To provide a method for low-cost chip package fabrication that can prevent a die from being contaminated. <P>SOLUTION: A chip package includes a base re-wiring layer 16 having an opening formed therein, an adhesive layer 24 having a window 26 formed therein free of adhesive material, and a die 12 affixed to the base re-wiring layer by way of the adhesive layer, the die being aligned with the window such that only a perimeter of the die contacts the adhesive layer. A shield element 20 is positioned between the base re-wiring layer and the adhesive layer and is generally aligned with the opening formed in the base re-wiring layer and the window of the adhesive layer such that only a perimeter of the shield element is attached to the adhesive layer. The shield element is separated from the die by an air gap and is configured to be selectively removable from the adhesive layer so as to expose the front surface 52 of the die. <P>COPYRIGHT: (C)2012,JPO&INPIT
申请公布号 JP2012069918(A) 申请公布日期 2012.04.05
申请号 JP20110158524 申请日期 2011.07.20
申请人 GENERAL ELECTRIC CO <GE> 发明人 PAUL ALAN MCCONNELEE;KEVIN MATTHEW DUROCHER;SCOTT SMITH;LAURA A PRINCIPE
分类号 H01L23/12;H01L27/14;H05K3/46 主分类号 H01L23/12
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