| 摘要 |
<P>PROBLEM TO BE SOLVED: To reduce parasitic capacitance between a gate and a source or drain of a dual-gate transistor. <P>SOLUTION: A semiconductor device comprises: a first insulation layer provided covering a first conductive layer; a first semiconductor layer provided on the first insulation layer; a second semiconductor layer provided on and separated from the first semiconductor layer so that the first semiconductor layer is exposed; an impurity semiconductor layer provided on the second semiconductor layer; a second conductive layer provided on the impurity semiconductor layer so that at least a part of the second conductive layer is in contact with the impurity semiconductor layer; a second insulation layer provided on the second conductive layer; a third insulation layer provided covering the first semiconductor layer, the second semiconductor layer, the impurity semiconductor layer, the second conductive layer, and the second insulation layer; and a third conductive layer provided on at least the third insulation layer. The third conductive layer overlaps with a part where the first semiconductor layer does not overlap with the second semiconductor layer, and also overlaps with a part of the second conductive layer. <P>COPYRIGHT: (C)2012,JPO&INPIT |
