| 摘要 |
<P>PROBLEM TO BE SOLVED: To suppress the increase of a circuit area and power consumption while improving the time resolution of a digital phase comparator. <P>SOLUTION: According to one embodiment, the digital phase comparator includes: a delay device column 200 for inputting reference signals Ref from an initial stage and giving delay in respective stages; a sampler group 100 including a sampler 100-0 for sampling signals CKV<SB POS="POST">0</SB>of N-phase input signals (N is an integer equal to or larger than 2) corresponding to the reference signals Ref and a sampler for sampling signals CKV<SB POS="POST">1</SB>whose phase is delayed by 2π/N compared to the signals CKV<SB POS="POST">0</SB>among the N-phase input signals corresponding to the output signals of the initial stage of the delay device column 200; and a detection circuit 300 for detecting a time difference of edges between the reference signals Ref and the signals CKV<SB POS="POST">0</SB>on the basis of the sample signals of the sampler group 100 and converting the time difference to a phase difference. <P>COPYRIGHT: (C)2012,JPO&INPIT |
