发明名称 Hardware dynamic cache power management
摘要 In an embodiment, a control circuit is configured to transmit operations to a circuit block that is being powered up after being powered down, to reinitialize the circuit block for operation. The operations may be stored in a memory (e.g. a set of registers) to which the control circuit is coupled. In an embodiment, the control circuit may also be configured to transmit other operations from the memory to the circuit block prior to the circuit block being powered down. Accordingly, the circuit block may be powered up or powered down even during times that the processors in the system are powered down (and thus software is not executable at the time), without waking the processors for the power up/power down event. In an embodiment, the circuit block may be a cache coupled to the one or more processors.
申请公布号 EP2437138(A2) 申请公布日期 2012.04.04
申请号 EP20110182547 申请日期 2011.09.23
申请人 APPLE INC. 发明人 MILLET, TIMOTHY J.;MACHNICKI, ERIK P.;BALKAN, DENIZ;GUPTA, VIJAY
分类号 G06F1/32;G06F12/0802 主分类号 G06F1/32
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