| 摘要 |
The invention provides a hardware accelerator module which is driven by a system processor via a system bus to sequentially process data blocks of a data stream in function of a parameter set defined by the processor, comprising a register block adapted to receive parameter sets from the system processor, an accelerator core adapted to receive streaming data, to process data blocks of said streaming data use in a manner defined by a parameter set, and to output processed streaming data, and a parameter buffering block adapted to consecutively store a plurality of parameter sets and to sequentially provide the parameter sets to the hardware accelerator core in function of a busy state of the hardware accelerator core. The parameter buffering block of the invention enables to reduce downtimes of hardware accelerators, to increase data throughput, and to reduce the risk of a processor overload in a processor which drives several hardware accelerators.
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