发明名称 |
Clock generator to reduce long term jitter |
摘要 |
A clock generator includes a controller, a digital phase locked loop (PLL) circuit, a charge pump phase locked loop (PLL) circuit and a divider. The controller generates a division factor and a first internal clock signal in response to a low-frequency reference clock signal and a multiplication factor. The digital PLL circuit generates a second internal clock signal in response to the reference clock signal, the division factor and the first internal clock signal. The charge pump PLL circuit generates a plurality of third internal clock signals by using the second internal clock signal. The divider generates a high-frequency clock signal in response to a phase selection signal, the division factor and the third internal clock signals. |
申请公布号 |
US8149030(B2) |
申请公布日期 |
2012.04.03 |
申请号 |
US20100691023 |
申请日期 |
2010.01.21 |
申请人 |
KIM CHUL-WOO;KIM WOO-SEOK;SONG MIN-YOUNG;PARK JAE-JIN;KIM JI-HYUN;KWAK YOUNG-HO;SAMSUNG ELECTRONICS CO., LTD.;KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATION |
发明人 |
KIM CHUL-WOO;KIM WOO-SEOK;SONG MIN-YOUNG;PARK JAE-JIN;KIM JI-HYUN;KWAK YOUNG-HO |
分类号 |
H03L7/06 |
主分类号 |
H03L7/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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