发明名称 Stacked field effect transistor configurations
摘要 An improved organization for a MOSFET pair mounts first and second FET dies in an overlying or stacked relationship to reduce the surface area‘footprint’of the MOSFET pair. The source and drain of a high side FEThigh and a low side FETlow or the drains of the respective high side FEThigh and low side FETlow are bonded together, either directly or through an intermediate conductive ribbon or clip, to establish a common source/drain or drain/drain node that functions as the switch or phase node of the device. The stacked organization allows for lower-cost packaging that results in a significant reduction in the surface area footprint of the device and reduces parasitic impedance relative to the prior side-by-side organization and allows for improved heat sinking.
申请公布号 US8148815(B2) 申请公布日期 2012.04.03
申请号 US20090424686 申请日期 2009.04.16
申请人 INTERSIL AMERICAS, INC. 发明人 GIRDHAR DEV A.;JOCHUM THOMAS A.;DUDUMAN BOGDAN M.
分类号 H01L23/24 主分类号 H01L23/24
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