发明名称 PACKAGE SUBSTRATE UNIT AND MANUFACTURING METHOD THEREFOR
摘要 <P>PROBLEM TO BE SOLVED: To provide a package substrate unit and manufacturing method therefor, capable of improving connection reliability between a solder bump on a semiconductor chip and a solder bump on a package substrate unit, with a narrowed pitch between solder bumps. <P>SOLUTION: A semiconductor chip mounting layer 20 of a package substrate unit 1 includes: an insulation layer 21; a conductive plating sheet layer 22a formed on the upper surface of the insulation layer 21; a conductive pad 23 formed on the upper surface of the conductive plating sheet layer 22a; a metallic post 24 formed in a substantially central portion of the conductive pad 23; and a solder resist layer 25 formed in a manner to enclose the conductive pad 23 and the metallic post 24. <P>COPYRIGHT: (C)2012,JPO&INPIT
申请公布号 JP2012064911(A) 申请公布日期 2012.03.29
申请号 JP20100232731 申请日期 2010.10.15
申请人 FUJITSU LTD 发明人 NANING NUE SAN;ARAI KAZUYA;FUKUI KEI;IKEGAMI SHINPEI;TAKAHASHI YASUHITO;YOSHIMURA HIDEAKI;SUZUKI HITOSHI
分类号 H01L23/12;H01L21/60 主分类号 H01L23/12
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