发明名称 METHODS OF FORMING FULLY EMBEDDED BUMPLESS BUILD-UP LAYER PACKAGES AND STRUCTURES FORMED THEREBY
摘要 Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include a die embedded in a coreless substrate, wherein a mold compound surrounds the die, and wherein the die comprises TSV connections on a first side and C4 pads on a second side of the die, a dielectric material on a first side and on a second side of the mold compound; and interconnect structures coupled to the C4 pads and to the TSV pads. Embodiments further include forming packaging structures wherein multiple dies are fully embedded within a BBUL package without PoP lands.
申请公布号 WO2012040735(A2) 申请公布日期 2012.03.29
申请号 WO2011US53325 申请日期 2011.09.26
申请人 INTEL CORPORATION;NALLA, RAVI K.;MANUSHAROW, MATHEW J.;MALATKAR, PRAMOD 发明人 NALLA, RAVI K.;MANUSHAROW, MATHEW J.;MALATKAR, PRAMOD
分类号 H01L23/48;H01L23/12;H01L23/485 主分类号 H01L23/48
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