| 摘要 |
A phase-locked loop based frequency synthesizer generates a plurality of output reference signals by phase-delaying an input reference signal and generates a plurality of comparison signals by using a signal having a frequency divided by the fractional frequency divider. Here, the comparison signals are lower than the divided frequency. Further, the phase-locked loop based frequency synthesizer controls an output frequency of a voltage controlled oscillator through phase and frequency comparison between the plurality of output reference signals and the plurality of comparison signals. |
