| 摘要 |
An A/D conversion device has first to third pulse delay circuits, first to third pulse passage stage detection circuits, a time output circuit, and an output circuit. Each of the first to third pulse delay circuit has multiple stages of delay units which are connected together and delay a first to a third pulse signals, respectively. Each of the first to third pulse passage stage detection circuit detects a first to a third number of stages, respectively. The time output circuit outputs a time signal. The output circuit outputs the digital value corresponding to the third number of stages.
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