| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a clock extraction circuit capable of extracting a stable clock with a digital logic circuit. <P>SOLUTION: The clock extraction circuit includes a counter (CNT) which is driven by an internal clock signal, and a control circuit (CTRL) comprising digital logic in which a counter value at next cycle is advanced more than one in normal or a current counter value is held according to advancement/delay of changes in reception data based on the monitoring result about presence of changes in the reception data as well as the counter value, for each cycle of the internal clock signal, and further, the reception data is controlled to be changed on the center side within a predetermined data change tolerable range of the counter value, and then, presence of inversion of the extracted clock signal at the next cycle is determined when the counter value is the predetermined value. <P>COPYRIGHT: (C)2012,JPO&INPIT |
