FUNCTIONAL UNIT FOR VECTOR LEADING ZEROES, VECTOR TRAILING ZEROES, VECTOR OPERAND 1S COUNT AND VECTOR PARITY CALCULATION
摘要
A method of performing vector operations on a semiconductor chip is described. The method includes performing a first vector instruction with a vector functional unit implemented on the semiconductor chip and performing a second vector instruction with the vector functional unit. The first vector instruction is a vector multiply add instruction. The second vector instruction is a vector leading zeros count instruction.
申请公布号
WO2012040539(A2)
申请公布日期
2012.03.29
申请号
WO2011US52889
申请日期
2011.09.23
申请人
INTEL CORPORATION;WIEDEMEIER, JEFF;SAMUDRALA, SRIDHAR;GOLLIVER, ROGER;MAHURIN, ERIC, W.
发明人
WIEDEMEIER, JEFF;SAMUDRALA, SRIDHAR;GOLLIVER, ROGER;MAHURIN, ERIC, W.