POLISHING PAD, POLYURETHANE LAYER THEREFOR, AND METHOD OF POLISHING A SILICON WAFER

摘要

A polyurethane layer for forming a polishing pad for a semiconductor wafer is described, wherein the polyurethane layer comprises: a foamed polyurethane, wherein the polyurethane foam has a density of about 640 to about 960 kg/m3, and a plurality of cells having an average diameter of about 20 to about 200 micrometers; and particles of a hydrophobic polymer having a critical surface energy of less than 35 mN/m and having a median particle size of 3 to 100 micrometers. Polishing pads as well as methods for polishing are also described.