发明名称 |
Fast ECC memory testing by software including ECC check byte |
摘要 |
The present invention relates to the architecture and operation of computer hardware memory logic, and in particular to a method and respective system for verifying hardware memory logic, wherein an Error Correction Code (ECC) is used for correcting single-bit or multi-bit errors when the ECC-bits cannot be accessed directly for a read or write process. The system and process employs the selection of data patterns that produce check bits that are all ones to ferret out errors in the ECC circuitry. |
申请公布号 |
US8145961(B2) |
申请公布日期 |
2012.03.27 |
申请号 |
US20080122753 |
申请日期 |
2008.05.19 |
申请人 |
ARNEZ ANDREAS;VOGT JOERG-STEPHAN;INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
ARNEZ ANDREAS;VOGT JOERG-STEPHAN |
分类号 |
G01R31/28;G11C29/00;G11C29/42;H03M13/00;H03M13/09 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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