发明名称 |
Latency control circuit, semiconductor memory device including the same, and method for controlling latency |
摘要 |
A latency control circuit includes a path calculator configured to calculate a delay value of a path that an input signal is to go through inside a chip and output the delay value as path information, a delay value calculator configured to output delay information representing a delay value for delaying the input signal based on a latency value of the input signal and the path information, and a delayer configured to delay the input signal by a delay corresponding to the delay information. |
申请公布号 |
US8144531(B2) |
申请公布日期 |
2012.03.27 |
申请号 |
US20090633387 |
申请日期 |
2009.12.08 |
申请人 |
CHOI HAE-RANG;KIM YONG-JU;HAN SUNG-WOO;SONG HEE-WOONG;OH IC-SU;KIM HYUNG-SOO;HWANG TAE-JIN;LEE JI-WANG;JANG JAE-MIN;PARK CHANG-KUN;HYNIX SEMICONDUCTOR INC. |
发明人 |
CHOI HAE-RANG;KIM YONG-JU;HAN SUNG-WOO;SONG HEE-WOONG;OH IC-SU;KIM HYUNG-SOO;HWANG TAE-JIN;LEE JI-WANG;JANG JAE-MIN;PARK CHANG-KUN |
分类号 |
G11C7/22 |
主分类号 |
G11C7/22 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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