Circuit for and method of minimizing power consumption in an integrated circuit device
摘要
A method of minimizing power consumption in an integrated device is disclosed. The method comprises providing a plurality of circuit blocks having circuits for performing logic functions, wherein each circuit block consumes power in a static state; coupling one of a plurality of operating voltages to each circuit block of the plurality of circuit blocks; enabling a reduction of power consumed by a first set of circuit blocks by way of a first power reduction signal; and enabling a reduction of power consumed by a second set of circuit blocks by way of a second power reduction signal. A circuit for minimizing power consumption in a device is also disclosed.
申请公布号
US8145923(B2)
申请公布日期
2012.03.27
申请号
US20080034361
申请日期
2008.02.20
申请人
LAKKAPRAGADA SHANKAR;LIEN SCOTT TE-SHENG;JANG TETSE;JENKINS, IV JESSE H.;NG MARK MEN BON;XILINX, INC.
发明人
LAKKAPRAGADA SHANKAR;LIEN SCOTT TE-SHENG;JANG TETSE;JENKINS, IV JESSE H.;NG MARK MEN BON