发明名称 Scan test circuit and scan test control method
摘要 A circuit includes a control flip-flop inputting a scan control signal and a scan path chain formed of scan storage elements serially connected. The scan path chain performs a shift operation as a first mode when the control flip-flop outputs a first status value, and performs a normal operation as a second mode when the control flip-flop outputs a second status value. When the scan control signal is switched from the first status value to the second status value, the control flip-flop outputs the second status value to the scan storage elements in synchronization with a first clock pulse, after the switching, of a clock provided to the scan storage elements. When the scan control signal is switched from the second status value to the first status value, the control flip-flop outputs the first status value to the scan storage elements at a timing of the scan control signal switching.
申请公布号 US8145964(B2) 申请公布日期 2012.03.27
申请号 US201113064612 申请日期 2011.04.04
申请人 MIKAMI KIYOSHI;RENESAS ELECTRONICS CORPORATION 发明人 MIKAMI KIYOSHI
分类号 G01R31/3177;G01R31/40 主分类号 G01R31/3177
代理机构 代理人
主权项
地址