发明名称 |
Integration of non-volatile charge trap memory devices and logic CMOS devices |
摘要 |
A semiconductor structure and method to form the same. The semiconductor structure includes a substrate having a non-volatile charge trap memory device disposed on a first region and a logic device disposed on a second region. A charge trap dielectric stack may be formed subsequent to forming wells and channels of the logic device. HF pre-cleans and SC1 cleans may be avoided to improve the quality of a blocking layer of the non-volatile charge trap memory device. The blocking layer may be thermally reoxidized or nitridized during a thermal oxidation or nitridation of a logic MOS gate insulator layer to densify the blocking layer. A multi-layered liner may be utilized to first offset a source and drain implant in a high voltage logic device and also block silicidation of the nonvolatile charge trap memory device. |
申请公布号 |
US8143129(B2) |
申请公布日期 |
2012.03.27 |
申请号 |
US20080185747 |
申请日期 |
2008.08.04 |
申请人 |
RAMKUMAR KRISHNASWAMY;KAPRE RAVINDRA;WARREN JEREMY;CYPRESS SEMICONDUCTOR CORPORATION |
发明人 |
RAMKUMAR KRISHNASWAMY;KAPRE RAVINDRA;WARREN JEREMY |
分类号 |
H01L29/792 |
主分类号 |
H01L29/792 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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