| 摘要 |
The present invention relates to a manufacturing method of a chip package, the method comprising: forming first leads and second leads, both having conductivity, on the top and bottom surfaces of a metal substrate; half-etching the top surface of the metal substrate to form a lead portion under the first leads and to form a die pad portion whose bottom is connected to the lead portion; attaching a chip onto the die pad portion and electrically connecting the chip and the first leads by a connector; forming an insulative molding portion on the metal substrate to bury the chip and the connector; and etching the bottom of the metal substrate to short-circuit the lead portion and the die pad portion, and a chip package manufactured using the same. Accordingly, the distance between a chip and first leads can be reduced by forming a conventional bump-shaped I/O pad in a lead shape, thus lead to cost reduction. Moreover, a large number of signal transmission systems can be reliably realized in a micro-pattern due to the lead shape. Moreover, the stability of the product can be improved by treating the thickness of the lead portion in the final step of the process. |
