| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a scan flip-flop capable of reducing the number of transistors without introducing a deterioration of an operation speed at the normal operation, and to provide a scan test circuit using this scan flip-flop. <P>SOLUTION: The scan flip-flop of this embodiment includes a selecting circuit and the flip-flop. The selecting circuit is equipped with a clocked inverter to be input with normal data and a transmission gate to be input with scan testing data to select and output any one of the normal data or the scan testing data. As for the flip-flop to be input with the output of the selecting circuit, a polarity of the output is normal rotation polarity to the normal data and is reversal rotation polarity to the scan testing data. <P>COPYRIGHT: (C)2012,JPO&INPIT |
