FREQUENCY DIVISION CIRCUIT AND PLL CIRCUIT COMPRISING SAME AND SEMICONDUCTOR INTEGRATED CIRCUIT

摘要

A frequency division circuit according to the present invention comprises: a variable-frequency divider (2) that outputs a first frequency-divided signal (c1) obtained by frequency division of a periodic signal (s5) at two different frequency division ratios; a counter circuit (3) that outputs a count value (c2) of the number of cycles of the first frequency-divided signal (c1) and restarts the counting operation from an initial value when reset; a comparator (4) that outputs, as a second frequency-divided signal, a pulse signal (s1) in which High and Low are inverted every time the count value (c2) matches a comparison reference value (a), that supplies this pulse signal to the variable-frequency divider (2) as a frequency-division-ratio switching signal, and that outputs a reset signal (r) to the counter circuit (3) every time the count value (c2) matches the comparison reference value (a); and a control circuit (5) that supplies the comparison reference value (a) to the comparator (4).