| 摘要 |
A nonvolatile memory device includes an array of rows and columns of memory cells and a plurality of word lines and bit lines associated with the memory cells. The memory device further includes a word line booster circuit coupled with the word lines for supplying a selected word line with the specific voltage as a drive voltage during an operation of the memory device, wherein the word line booster circuit includes a first boosting capacitor and a second boosting capacitor connected in parallel each other adapted to generate a boosting voltage and a first precharge circuit for precharging the first boosting capacitor and the second boosting capacitor. the word line booster circuit further includes a third boosting capacitor operatively connected to the first boosting capacitor and the second boosting capacitor via a charge-sharing transistor, the third boosting capacitor being connected to one end of a load resistor to generate an output signal at the other end of the load resistor when the charge sharing transistor is enabled. In addition, the word line booster circuit includes a high voltage detector to generate a detecting signal in response to a control signal from an address transition detector and the output signal generated by the third boosting capacitor and load resistor and a clock control circuit adapted to enable the charge sharing transistor and to disable one of the first boosting capacitor and the second boosting capacitor upon receiving the control signal from the address transition detector and the detecting signal from the voltage detector. The word line booster circuit further includes a discharge circuit to discharge the boosting voltage at a node connected to the third boosting capacitor. |
