| 摘要 |
<P>PROBLEM TO BE SOLVED: To quicken a write/read operation while ensuring reliability of data. <P>SOLUTION: A memory controller has: a data control circuit which performs input/output of write/read data with a host device and generates a write strobe signal; and an adjustment circuit for executing at least one of a first process for generating a write strobe adjustment signal designating the timing to fetch write data through each memory access unit by adjusting for each memory access unit the timing of the write strobe signal generated by the data control circuit during a write operation and a second process for generating a read strobe adjustment signal designating the timing to read out read data read from each memory access unit through a data control section by adjusting for each memory access unit the timing of a read strobe signal generated by a memory device during a read operation. <P>COPYRIGHT: (C)2012,JPO&INPIT |
