| 摘要 |
In one embodiment, the present invention includes a logic having a first link interface to enable communication with an intellectual property (IP) logic adapted on a single semiconductor die with the logic, where the IP logic includes a second link interface coupled to the first link interface via an on-die interconnect. In this way, the IP logic can be unmodified with respect to a standalone device having the IP logic incorporated therein. Other embodiments are described and claimed.
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