| 摘要 |
<P>PROBLEM TO BE SOLVED: To efficiently merge processing of a sequential execution processor (RISC processor 100) with processing of a parallel execution processor (VLIW coprocessor 200). <P>SOLUTION: Of four instructions simultaneously fetched on a RISC processor 100, specific fields of second and fourth instructions are predecoded by an instruction predecoder 170. The specific field includes an operation code field and a simultaneously issuable instruction count field. If the operation code filed indicates a VLIW coprocessor instruction, a program counter management portion 110 controls an increment value of a program counter in accordance with the simultaneously issuable instruction count filed. In the VLIW coprocessor 200, the VLIW coprocessor instruction is executed according to a degree of parallelism in accordance with the simultaneously issuable instruction count field. <P>COPYRIGHT: (C)2012,JPO&INPIT |
