发明名称 VARIABLE FIELD ADDER
摘要 A technique for adding fields or portions in a fixed word adding system with carry-in and carry-out signals being as if two complete words are added together. A masking register causes two logic circuits to pass particular fields of corresponding words in two word registers. The logic circuits operate to fill the digits of one word outside of the field of that word with binary "1" signals and corresponding digits of the other word with binary O's. The sum of each digit which appears in the adder is a binary "1" so that a carry-in signal may be injected at the lowest order bit position of the adder and extracted from the highest order bit position of the adder in a normal manner. The masking register controls a further logic circuit so that only the added fields are read out of the adder.
申请公布号 US3683163(A) 申请公布日期 1972.08.08
申请号 USD3683163 申请日期 1969.08.20
申请人 INTERN. COMPUTERS LTD. 发明人 TREVOR WILLIAM HANSLIP
分类号 G06F7/50;G06F7/505;(IPC1-7):G06F7/28;G06F7/38 主分类号 G06F7/50
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