| 摘要 |
According to one embodiment, a DRAM controller includes a clock generating and switching unit for supplying a first clock to a DRAM in a normal operation and generating a second clock having a lower speed than the first clock and supplying the generated second clock to the DRAM in an initialization processing, and a DRAM access circuit having a DLL circuit for regulating a fetch timing of data output from the DRAM based on the first clock, and fetching, in a fetch timing regulated by the DLL circuit, data output from the DRAM in a timing based on the second clock in relation to the initialization processing and the transfer data output from the DRAM in a timing based on the first clock in the initialization processing and the normal processing, respectively.
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