发明名称 CLOCK MARGIN TEST SYSTEM, METHOD AND CORRESPONDING DEVICE
摘要 <p>A clock margin test system, method and corresponding device are disclosed in the present invention. The system includes that a clock margin adjustment device, a product system under test and a product performance parameter monitoring device are connected successively. The clock margin adjustment device is set as receiving a clock signal output by a driving clock source of the product system under test, adjusting the reference level and / or amplitude of the clock signal, performing a butt matching processing on the adjusted clock signal, so as to generate the clock signal for butt-matching with the product system under test, and then output the clock signal; the product system under test is set as inputting the clock signal output by the driving clock source of the product system under test into the clock margin adjustment device, receiving the clock signal output by the clock margin adjustment device and providing it as a driving clock to the part, which requires the driving clock, of the product system under test; the product performance parameter monitoring device is set as monitoring the performance parameter of the product under test when the part, which requires the driving clock, of the product system under test works under driving of the driving clock.</p>
申请公布号 WO2012034407(A1) 申请公布日期 2012.03.22
申请号 WO2011CN74377 申请日期 2011.05.20
申请人 ZTE CORPORATION;XIAO, YONG;HUANG, JIAN 发明人 XIAO, YONG;HUANG, JIAN
分类号 H04B17/00 主分类号 H04B17/00
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