发明名称 METHOD FOR LOWERING POWER LOSS AND CIRCUIT
摘要 A method and circuit for suppressing a bias current and decreasing power consumption. A current suppression circuit is coupled to a circuit element, which is capable of conducting the bias current. Coupling the current suppression circuit to the circuit element forms a node. In one operating mode, the current suppression circuit applies a voltage to the node in response to a heavy load. In another operating mode, the current suppression circuit lowers the voltage at the node in response to a light load or no load. Lowering the voltage at the node decreases the flow of bias current through the circuit element thereby lowering power loss.
申请公布号 US2012069609(A1) 申请公布日期 2012.03.22
申请号 US200913264153 申请日期 2009.06.10
申请人 CHRISTOPHE BASSO;LOUVEL JEAN-PAUL 发明人 CHRISTOPHE BASSO;LOUVEL JEAN-PAUL
分类号 H02M3/335 主分类号 H02M3/335
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