发明名称 |
PREFETCH ADDRESS HIT PREDICTION TO REDUCE MEMORY ACCESS LATENCY |
摘要 |
A prefetch unit receives a memory read request having an associated address for accessing data that is stored in memory. A next predicted address is determined in response to a prefetch address stored in a slot of an array for storing portions of predicted addresses and associated with a slot in accordance with an order in which a prefetch FIFO counter is modified to select the slots of the array. Data is prefetched from a lower-level hierarchical memory in accordance with a next predicted address and provisioned the prefetched data to minimize a read time for reading the prefetched data. The provisioned prefetched data is read-out when the address of the memory request is associated with the next predicted address. |
申请公布号 |
US2012072672(A1) |
申请公布日期 |
2012.03.22 |
申请号 |
US201113212980 |
申请日期 |
2011.08.18 |
申请人 |
ANDERSON TIMOTHY D.;ZBICIAK JOSEPH R. M.;PIERSON MATTHEW D. |
发明人 |
ANDERSON TIMOTHY D.;ZBICIAK JOSEPH R. M.;PIERSON MATTHEW D. |
分类号 |
G06F12/08 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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