| 摘要 |
<P>PROBLEM TO BE SOLVED: To shorten access time of cache memory while securing a timing margin and enabling acceleration. <P>SOLUTION: A cache memory control device comprises: a first clock synchronization part 16A for using a first clock to synchronize an address 1 and a data way that are supplied to a data cache memory 20A, and for supplying the synchronized address 1 and data way to the data cache memory along with the first clock signal; a second clock synchronization part 16B for using a second clock signal to synchronize an address 2 and a tag way that are supplied to a tag cache memory 20B, and for supplying the synchronized address 2 and tag way to the tag cache memory along with the second clock signal; and an address comparison part 11-1/2 for comparing a tag of multiple ways with an address of a predetermined bit field of an access address to CPU to determine whether they are consistent or inconsistent. A frequency of the second clock signal is set higher than that of the first clock signal. <P>COPYRIGHT: (C)2012,JPO&INPIT |
