发明名称 |
Integrated Circuit Package With Reduced Parasitic Loop Inductance |
摘要 |
A multi-layer integrated circuit package includes a switched-mode power supply circuit including a plurality of transistors which form part of a main current loop of the switched-mode power supply circuit. The plurality of transistors are arranged in one or more layers of the integrated circuit package. The package further includes a conductive plate arranged in a different layer of the integrated circuit package than the plurality of transistors. The conductive plate is in close enough proximity to at least part of the main current loop so that a current can be electromagnetically induced in the conductive plate responsive to a change in current in the main current loop. |
申请公布号 |
US2012068681(A1) |
申请公布日期 |
2012.03.22 |
申请号 |
US20100887928 |
申请日期 |
2010.09.22 |
申请人 |
EJURY JENS;INFINEON TECHNOLOGIES NORTH AMERICA CORP. |
发明人 |
EJURY JENS |
分类号 |
G05F3/02;H01L21/00 |
主分类号 |
G05F3/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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