发明名称 |
PATTERNING A SINGLE INTEGRATED CIRCUIT LAYER USING AUTOMATICALLY-GENERATED MASKS AND MULTIPLE MASKING LAYERS |
摘要 |
A multiple mask and a multiple masking layer technique can be used to pattern an IC layer. A RET can be used to define one or more fine-line patterns in a first masking layer. Portions of the fine-line features are then removed or designated for removal using a mask. This removal/designation can include accessing a desired layout (with at least one layout feature including a fine-line feature and a coarse feature) and expanding layout features only in directions along critical dimensions of those layout features. Another mask can then be used to define coarse features in a second masking layer formed over the patterned first masking layer. Coarse feature(s) can be derived from the desired layout using a shrink/grow operation performed only in directions orthogonal to a critical dimension of the fine-line features. The IC layer can be patterned using the composite mask formed by the patterned first and second masking layers. |
申请公布号 |
EP2430650(A1) |
申请公布日期 |
2012.03.21 |
申请号 |
EP20090736559 |
申请日期 |
2009.09.01 |
申请人 |
SYNOPSYS, INC. |
发明人 |
LIU, TSU-JAE KING |
分类号 |
H01L21/027;G03F1/00;G03F1/36;G03F7/00;G03F7/20 |
主分类号 |
H01L21/027 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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