| 摘要 |
A protected monolithic integrated flip-flop circuit comprises a pair of NPN transistors as the active flip-flop elements with the collectors of each of these transistors being supplied from a constant current source in the form of a dual-collector lateral PNP transistor. Collector-to-substrate distributed capacitance operates to retard the switching time of the flip-flop causing it to be a low speed flip-flop. A pair of substrate PNP transistors are used to apply the input trigger signals to the NPN transistors and operate to provide protection for the circuit against high positive or negative input voltages.
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