发明名称 |
LOAD/STORE DISJOINT FACILITY AND INSTRUCTION THEREFORE |
摘要 |
<p>A Load/Store Disjoint instruction, when executed by a CPU, accesses operands from two disjoint memory locations and sets condition code indicators to indicate whether or not the two operands appeared to be accessed atomically by means of block-concurrent interlocked fetch with no intervening stores to the operands from other CPUs. In a Load Pair Disjoint form of the instruction, the accesses are loads and the disjoint data is stored in general registers.</p> |
申请公布号 |
EP2430525(A1) |
申请公布日期 |
2012.03.21 |
申请号 |
EP20100776354 |
申请日期 |
2010.11.08 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
MITRAN, MARCEL;SLEGEL, TIMOTHY;JACOBI, CHRISTIAN;WEBB, CHARLES |
分类号 |
G06F9/312;G06F9/30;G06F9/38 |
主分类号 |
G06F9/312 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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