| 摘要 |
A switched capacitor sigma-delta modulator or another analog-to-digital converter (ADC) uses chopper stabilization. Chopping clock transitions are performed during non-active periods of the sampling clock phases, reducing disturbance of the circuit caused by chopping and increasing the time available for settling of the circuit given a particular sampling frequency. An asynchronous state machine may govern sampling and chopping clock transitions. In embodiments, inactive transition of a first sampling clock causes inactive transition of a second chopping clock, which in turn causes active transition of a first chopping clock. The next inactive transition of the first sampling clock causes inactive transition of the first chopping clock, which causes an active transition of the second chopping clock. |
