| 摘要 |
A memory interface module provides interfacing between a host processor with multiple flash memories and parallel interfaces of varying protocols. The interface module includes multiple register files, multiple operation information registers, an internal memory, a flash interface portion, and a finite state machine (FSM). The register files receive a command from the host processor for controlling an operation of multiple flash memories. The operation information registers execute and store the command and operation information. The internal memory receives and stores host data from the host processor. The internal memory further stores flash data extracted from multiple flash memories. The flash interface portion interacts with the memory devices connected to the controller. The FSM extracts the command and the operation information from the register files, which are programmed by the user and controls the control signals of the memory devices connected to the controller through the flash interface. |
