发明名称 Integrated circuits, systems, and methods for reducing leakage currents in a retention mode
摘要 An integrated circuit includes at least one memory array for storing data. A first switch is coupled with the memory array. A first power line is coupled with the first switch. The first power line is operable to supply a first power voltage. A second switch is coupled with the memory array. A second power line is coupled with the second switch. The second power line is operable to supply a second power voltage for retaining the data during a retention mode. A third power line is coupled with the memory array. The third power line is capable of providing a third power voltage.
申请公布号 US8139436(B2) 申请公布日期 2012.03.20
申请号 US20100716363 申请日期 2010.03.03
申请人 CHEN YEN-HUEI;LEE CHENG HUNG;TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. 发明人 CHEN YEN-HUEI;LEE CHENG HUNG
分类号 G11C5/14 主分类号 G11C5/14
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