发明名称 |
DIRECT MEMORY ACCESS CACHE PREFETCHING |
摘要 |
An apparatus having a first cache and a controller is disclosed. The first cache may be configured to assert a first signal after receiving given information in response to being ready to receive additional information. The controller may be configured to (i) fetch the given information from a memory to the first cache and (ii) prefetch first information in a direct memory access transfer from the memory to the first cache in response to the assertion of the first signal.
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申请公布号 |
US2012066456(A1) |
申请公布日期 |
2012.03.15 |
申请号 |
US20100882515 |
申请日期 |
2010.09.15 |
申请人 |
RABINOVITCH ALEXANDER;DUBROVIN LEONID |
发明人 |
RABINOVITCH ALEXANDER;DUBROVIN LEONID |
分类号 |
G06F12/08;G06F12/00 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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