发明名称 SIMULATED WIREBOND SEMICONDUCTOR PACKAGE
摘要 A semiconductor package with simulated wirebonds. A substrate is provided with a plurality of first pads on a first surface and a plurality of second pads on a second surface. Each of the first pads are electrically coupled to one or more of the second pads. At least one semiconductor device is located proximate the first surface of a substrate. The simulated wirebonds include at least a first dielectric layer selectively printed to create a plurality of recesses, and a conductive material located in the recesses to form first and second contact pads, and electrical traces electrically coupling the first and second contact pads. The first contact pads are electrically coupled to terminals on the semiconductor device and the second contact pads are electrically coupled to the first pads on the first surface of the substrate. An overmolding material seals the semiconductor device and the simulated wirebonds
申请公布号 US2012061851(A1) 申请公布日期 2012.03.15
申请号 US201013319120 申请日期 2010.06.07
申请人 HSIO TECHNOLOGIES, LLC 发明人 RATHBURN JAMES
分类号 H01L23/48;H01L21/56 主分类号 H01L23/48
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